In manufacturing a semiconductor device, there has been used photolithography as a patterning technique for forming a circuit pattern on a semiconductor wafer (hereinafter, simply referred to as “wafer”) as a processing target substrate. In order to form the circuit pattern by using photolithography, a resist film is formed on a wafer by coating the wafer with a resist solution, the resist film is exposed to lights irradiated onto the resist film so as to correspond to the circuit pattern, and then the exposed resist film is developed.
Recently, as a semiconductor device is operated at high speed and tends to be highly integrated, a circuit pattern formed on a wafer is required to be miniaturized by a patterning technique using photolithography. For this reason, conventionally, light of a shorter wavelength has been used for an exposure process, but it is not sufficient for an ultra-miniaturized semiconductor device after 45 nm node.
Here, as a patterning technique used for the ultra-miniaturized semiconductor device after 45 nm node, it has been proposed that when a pattern is formed on a single layer, patterning using photolithography is performed a plurality of times (see, for example, Patent Document 1). For example, double patterning is a technique of performing patterning process two times.
One of double patterning techniques is a lithography lithography etching (LLE) process. In the LLE process, a first resist pattern is formed by performing a first patterning process and a second resist pattern is formed by performing a second pattering process, and an etching process is performed by using the first and second resist patterns as masks.    Patent Document 1: Japanese Patent Laid-open Publication No. H07-147219
However, if resist patterns are formed by performing double patterning such as the above-described LLE process, there is a following problem.
In the first patterning process, a first resist film is formed on a wafer and then exposed and developed, so that the first resist pattern is formed. Thereafter, in the second patterning process, a second resist film is formed on the wafer, on which the first resist film is formed, and then exposed and developed, so that the second resist pattern is formed.
Here, after the development process of the first patterning process, a cleaning process is performed. However, if the cleaning process is not performed sufficiently, there may occur a development failure in the development process of the second patterning process, which may result in non-uniformity in line widths of the second resist pattern. Particularly, the line widths of the second resist pattern are not uniform between a central area of the wafer and a periphery area of the wafer.
By way of example, in order to sufficiently perform the cleaning process, it is desirable that a sufficiently long time be spent on the cleaning process. However, the sufficiently long time for the cleaning process may increase a time for processing a single sheet of a wafer, i.e., a so-called “tact time”, and, thus, the number of processed wafers per unit time may decrease and productivity may be lowered.